Step-by-Step Thermal Via D… | PCBA & EMS Insights

The Heat Problem in High-Current 4-Layer Boards — Why Thermal Vias Aren't Optional

When your 4‑layer PCB carries 10 A, 20 A, or more on internal power planes and buried traces, the copper isn’t just a conductor — it’s a heating element. Standard trace width calculators give you a current‑carrying capacity based on a conservative temperature rise, often 10 °C or 20 °C, but they assume the heat can escape freely. In a laminated stackup, inner layers are thermally choked. FR‑4 has a thermal conductivity around 0.3 W/m·K, while copper is nearly 400 W/m·K. That means heat generated on an inner 1‑oz copper plane has nowhere to go except through the dielectric — slowly.

The result: local hotspots that raise the trace’s electrical resistance, which in turn feeds more heat. I²R losses spiral. At sustained high current, you can easily push an internal trace past its rated temperature limit, degrade laminate adhesion, and eventually cause blistering or delamination. IPC‑2152, “Standard for Determining Current‑Carrying Capacity in Printed Board Design,” provides derating guidance for internal layers, but even following those charts doesn’t guarantee thermal safety unless you actively move heat out of the board. This is where thermal vias become critical. They aren’t cosmetic drill‑fills; they are solid copper‑plated cylinders that create low‑impedance heat paths from inner copper to outer planes, where convection, radiation, and heatsinking can actually remove energy. High‑current 4‑layer boards without a deliberate thermal‑via strategy represent a reliability risk — one that often shows up only during thermal cycling or after months in the field.

IPC standards such as IPC‑2221 and IPC‑2152 have long recognized the necessity of thermal management, and the industry treats thermal vias as the primary, cost‑effective solution for conducting heat away from hot copper layers before temperature rise compromises the PCB’s structural and electrical integrity.

How a Thermal Via Conveys Heat Away from Hot Copper — The Physics and Parameters

Think of a thermal via as a heat pipe without the phase change. Heat flows from a wide internal trace into the plated barrel of the via, travels through the 25 µm (or thicker) copper lining, and dumps into a large copper area on an outer layer or an internal plane. The thermal resistance network includes the constriction resistance at the trace‑to‑via junction, the barrel conduction, and the spreading resistance into the destination plane. Because copper’s thermal conductivity is high, the limiting element is usually the via barrel itself and the number of vias you place in parallel.

The effective thermal resistance of a single via depends mainly on its drill diameter and plating thickness. A larger diameter means more copper cross‑section for heat flow, but also demands more board real estate. Standard 1‑oz plating (about 35 µm) isn’t always achievable in small holes without special processes; most fabs deliver 20–25 µm in the barrel. The table below captures the thermal resistance for three common via sizes with 25 µm plating, along with a practical rule for how many vias you need in parallel to keep the temperature rise below 20 °C per watt of dissipated power.

Drill Diameter (mm)	Plating Thickness (µm)	Approx. Thermal Resistance ( °C/W)	Vias per Watt for ΔT ≤ 20 °C	Notes
0.3	25	55–65	3	Smallest practical size; high resistance
0.5	25	28–35	2	Good balance of density and thermal path
0.8	25	16–22	1	Larger land requirement; very efficient

These numbers assume the via is thermally bonded to a plane at both ends with unrestricted copper pours. In reality, annular rings and anti‑pad sizing — governed by IPC‑2221 — impose constraints. For a Class 2 board, the minimum annular ring is typically 0.05 mm, meaning a 0.3 mm via requires a 0.4 mm pad. You need enough copper land to transfer heat laterally without choking the path. Always verify that your ECAD design rules account for the minimum annular ring and that the plating thickness meets IPC‑6012 Class 2 or 3 requirements. When you’re pushing 20 A through an internal plane, doubling the via count is often simpler — and more reliable — than guessing at the exact thermal resistance.

Open Vias, Tented, Capped, or Filled? Selecting a Finish That Won't Wreck Assembly

How you finish a thermal via determines whether it becomes a reliable heat path or an assembly headache. The choice influences solder wicking, voiding in SMT joints, and the long‑term mechanical integrity of the via barrel. The table below compares the four most common treatments you’ll specify on your fabrication drawing.

Treatment	Thermal Path Through Via	Solder Wicking Risk	Assembly Compatibility	Relative Cost
Open (untented)	Copper barrel; air in center adds negligible conduction	High — solder can flow in	Poor for via‑in‑pad; fine for standalone connections	Lowest
Tented one side (solder mask)	Same as open; mask blocks wicking on one side	Moderate — other side remains open	Better, but not enough for pad‑in‑via without fill	Low
Epoxy‑filled (non‑conductive)	Copper barrel dominates; fill conductivity ~0.2–1 W/m·K	Eliminated — flat surface after planarization	Excellent for via‑in‑pad if over‑plated; suitable for most SMT	Medium
Copper‑filled (conductive)	Barrel plus solid copper fill; effective conductivity >300 W/m·K	Eliminated — solid copper plug	Best for high‑power devices; allows direct via‑in‑pad under power FETs	High

For moderate‑power designs where the via is not directly under a component pad, tenting the via on one side often suffices to prevent wicking. However, if you’re placing a 4‑layer board’s thermal vias directly beneath a power MOSFET, GaN transistor, or a large‑package diode to extract heat into a bottom‑side heatsink, you must specify filled and capped vias. Untented vias in this location will pull solder away from the component pad, creating voids and increasing thermal resistance at the joint. Nova PCBA processes filled and capped vias routinely, supporting both epoxy‑fill with copper over‑plating and solid copper‑fill processes. Engage them early for DFM feedback — the filler material and plating thickness should be locked before you finalise the stackup.

Step-by-Step Design Workflow: Placing, Sizing, and Checking Thermal Vias in Your ECAD Tool

Integrating thermal vias into a high‑current 4‑layer board is not an afterthought; it’s a deliberate ECAD exercise that ties mechanical layout, electrical performance, and thermal simulation together. Here is a proven workflow that has saved countless re‑spins on power converter and motor driver boards.

Estimate total power dissipation per hot region. Use your circuit simulation or measurements to determine how many watts will be lost in each internal trace or plane segment. For a 2‑oz inner plane carrying 15 A with 10 mΩ resistance, that’s 2.25 W.
Calculate the rough via count using a conservative rule. For 0.5 mm vias with standard 25 µm plating, assign one via per 0.5 W to 0.7 W if you need a ≤20 °C temperature rise. For the 2.25 W example, you’d need 4–5 vias directly under the hotspot.
Place vias as close as physically possible to the heat source. Group them in a tight array, not scattered. The thermal spreading resistance in the copper plane increases with distance, so proximity matters more than symmetry.
Connect the via pads to all available copper layers. On a 4‑layer board, you typically have top and bottom copper pours plus an internal ground plane. Create thermal “spokes” or direct copper connections to every layer. Do not leave a via connected only to one plane — every additional connection lowers thermal resistance.
Configure design rules to handle annular rings and isolation. Follow IPC‑2221 recommendations: for a 0.5 mm hole, a 0.9 mm pad provides a 0.2 mm annular ring, comfortable for Class 2. Set the via‑to‑trace spacing to at least 0.15 mm to prevent solder mask bridging and maintain dielectric integrity.
Define the thermal relief connections for outer planes. While internal planes benefit from direct connection, outer plane pours may need thermal relief spokes to prevent excessive heat sinking during soldering — but only on layers that don’t serve as the primary heatsink. On the heatsink side, use direct solid connections and rely on the assembly profile to manage soldering.
Run a design rule check (DRC) and a connectivity check. Verify that every thermal via actually touches the intended nets and that there are no unconnected pads. A single floating via can become a localized hotspot because it won’t conduct heat to the outer planes.
Perform a thermal simulation if possible. Even a simple 2D finite‑difference model in your ECAD tool or an external solver (like Ansys Icepak or open‑source options) will reveal whether the via array is sufficient. Adjust via count or drill size based on the predicted junction temperature.

The table below summarizes the critical design parameters you’ll set in your constraint manager, applicable to most high‑current 4‑layer boards.

Parameter	Recommended Value	Why It Matters
Drill diameter (thermal via)	0.4–0.6 mm	Balances thermal resistance and board space
Pad diameter	Drill + 0.2 mm (min. annular ring)	IPC‑2221 Class 2 annular ring requirement
Via‑to‑trace clearance	≥0.15 mm	Prevents electrical leakage and etching issues
Plating thickness	20–25 µm (Class 2); 25–30 µm (Class 3)	Ensures adequate thermal and electrical conduction
Thermal spoke width (outer layer)	0.25–0.35 mm, 4 spokes	Aids soldering without excessive thermal choking
Inner plane connection	Direct (solid) connection	Minimizes thermal resistance to plane
Fill process (if via‑in‑pad)	Epoxy fill + copper over‑plating or Cu fill	Avoids solder wicking; enables reliable SMT

Before releasing the Gerber files, share your board with the assembly partner. Nova PCBA offers DFM reviews that specifically catch via‑in‑pad risks, insufficient annular rings, and marginal plating thicknesses. A 15‑minute consultation can prevent a full prototype failure.

Thermal Via Questions That Come Up After the First Prototype

Even engineers who follow design guides encounter real‑world surprises. The following answers draw from field experience and IPC guidelines to address the most common post‑prototype questions about thermal vias in 4‑layer high‑current designs.

Q: How many thermal vias do I need for a 10 A trace on a 4‑layer board?
It depends on trace width, copper weight, and via diameter, but a practical rule‑of‑thumb: each 0.3 mm via with 25 µm plating can thermally relieve about 0.5–1.0 A when connected to a large plane. For a 10 A trace, plan on 10–20 vias clustered close to the heat source. Verify the temperature rise with a thermal simulation or an infrared measurement on the first board. If you can increase the via diameter to 0.5 mm, you can cut that number in half. Always oversize the via array — copper is cheap, board failures are not.

Q: Should I fill thermal vias with conductive or non‑conductive epoxy?
Conductive epoxy (copper‑filled) offers far better thermal conductivity — effective values above 300 W/m·K compared with 0.2–0.8 W/m·K for non‑conductive fill. This makes copper‑filled vias the preferred choice when the via is directly under a power semiconductor’s thermal pad, because the fill itself becomes a major heat transfer path. Non‑conductive epoxy, on the other hand, excels at preventing solder wicking and is sufficient for many moderate‑power designs where the via’s copper barrel already provides enough thermal relief. Balance your thermal budget, assembly capability, and cost. Discuss your requirements with your CM; Nova PCBA can guide you toward the most cost‑effective fill process that meets your performance targets.

Q: What IPC standard governs thermal via design?
IPC‑2221 (Generic Standard on Printed Board Design) defines via aspect ratios, annular rings, and spacing — the mechanical backbone of any via. IPC‑6012 sets the quality and plating thickness requirements for the finished board. For high‑current applications, you must also consult IPC‑2152, which provides current‑temperature derating charts and explicitly highlights the role of copper area and thermal vias in managing temperature rise. A robust design references all three: IPC‑2221 for physical design, IPC‑6012 for fabrication quality, and IPC‑2152 for thermal performance.

Q: Can I use via‑in‑pad for thermal vias under a power FET?
Yes, but untreated via‑in‑pad creates a direct route for liquid solder to wick into the via barrel during reflow, starving the pad‑to‑lead joint and leaving voids that increase thermal resistance. To avoid this, specify filled and capped vias — either epoxy‑fill with a copper over‑plate (capped) or solid copper fill. These methods create a flat, non‑wicking pad surface that can be soldered reliably. Nova PCBA processes both types and can advise on the right specification for your pad size and thermal load. Confirm with your CM before finalizing the layout; not all manufacturers can handle tight‑pitch micro‑via filling.

Q: Does reducing the via plating thickness hurt thermal performance?
Significantly. Thinner plating increases the effective thermal resistance because less copper is available to conduct heat along the barrel. A 10 µm plating, sometimes pushed by fabs to reduce cost, can cut the thermal conductance by over half compared with standard 25 µm plating. For high‑current 4‑layer designs, maintain at least 20–25 µm of copper in the barrel, as required by IPC Class 2. Never trade plating thickness for cost savings on a thermal‑critical board; the resulting hotspot can degrade laminate adhesion and lead to field failures that far exceed the pennies saved in fabrication.

Conclusion — Thermal via design for high‑current 4‑layer PCBs is a cross‑discipline task that blends heat transfer physics, IPC design rules, and assembly process requirements. Starting with a realistic power dissipation estimate, choosing the right via diameter and count, and specifying an appropriate fill treatment are the pillars of a robust thermal strategy. Engaging a manufacturing partner early — one that understands both bare‑board fabrication and SMT assembly — makes the difference between a first‑pass success and a costly re‑spin. Nova PCBA supports the entire chain, from DFM review of thermal via arrays to filled and capped via‑in‑pad processes, helping you turn a hot inner layer into a managed, reliable power path.

Step-by-Step Thermal Via Design for High-Current 4-Layer PCBs